Digital binary counters are widely used in digital information processing systems. In general, a digital binary counter is formed from logic circuitry that includes N binary stages having respective bit outputs that change state in response to input pulses received at the counter. The states of the respective bit outputs change in accordance with a binary code that represents numerical values between 0 and 2N−1. Consequently, the digital binary counter can be used to generate a binary code that corresponds to a count of the number input pulses received at the counter over a predetermined interval.
One type of digital binary counter is a monotonic or serial binary counter, which generates what is commonly referred to as a natural binary code. As is well known in the art, in a serial binary counter more than one of the N binary stages can change state at a time in response to a single counter input pulse. To obtain an accurate counter reading, the bit outputs of the respective N binary stages should be sampled at a time when none of the binary stages is changing state. Consequently, if there is a slight misalignment in the time of sampling of the bit outputs of the serial binary counter, or if there is a need to sample the bit outputs of the serial binary counter at a time when several of the binary stages are changing state, a large error can occur in the counter reading. FIG. 1A illustrates a natural binary code waveform 10 that a nine bit serial counter would generate. Referring to FIG. 1A, if the bit outputs Q were sampled at a time t0, which corresponds to a time that all nine of the binary stages of the counter are changing state, the potential error in the counter reading can be up to half scale or 28.
Another type of digital counter is a gray binary code counter, which generates what is commonly referred to as a gray code. As is also well known in the art, the logic circuitry of a gray binary code counter differs from that a serial binary code counter in that only one of the binary stages can change state at a time for each counter input pulse. Therefore, the potential error in reading a gray code is independent of sampling time and is only between which of two adjacent count values are correct. FIG. 1B illustrates a gray code waveform 12 that a nine bit gray code binary counter would generate. For purposes of comparing potential counter read errors, the waveforms 10 and 12 are aligned to show the bit outputs that would be generated based on receipt of the same counter input pulses. Referring to FIGS. 1A and 1B, assuming that a counter needs to be read at about the time to, the counter read error is likely to be much greater for the serial binary counter than the gray code counter. See U.S. Pat. Nos. 4,618,849 and 4,937,845, incorporated by reference herein, for a discussion of gray code counter and serial binary counter construction and operation.
In many digital binary counter applications, the bit outputs of the binary counter need to be sampled asynchronously and the counter reading that is obtained must have a minimum of error. These digital binary counter applications, therefore, call for use of a gray code binary counter logic circuitry implementation. For example, an infrared detector focal plane array (“FPA”) device typically includes a gray code binary counter to facilitate very accurate detection of an image by imaging pixels. In the FPA, the gray code counter functions to extend the dynamic range of an imaging pixel, which has a linear response characteristic that is relatively limited in range, and also lowers the required pixel read out rate. During operation of the FPA, the pixel in the FPA is reset, i.e., the input charge (detected infrared light energy) is discharged, once the amount of input charge reaches a predetermined level that corresponds to or is near the upper limit of the linear response range for the pixel. The gray code counter in the FPA counts the number of times that a pixel is reset within a fixed interval. The bit outputs of the counter are asynchronously sampled at the end of a successive fixed interval to obtain a gray code reading. The highly precisely counter value corresponding to the gray code reading is then used to compute, with great accuracy, the amount of input charge that the pixel absorbed over the fixed interval. Accordingly, the counts for the respective pixels of the array are used to reconstruct the image (infrared light energy) present in front of the FPA during the fixed interval.
Prior art gray code binary counters, however, are logically complex and require substantial amounts of logic gating in their implementation. For example, referring to FIG. 2, a typical prior art gray code counter 20 having 2N count capability includes N stages of D-type flip-flops 22 and additional logic circuitry, such as an exclusive-OR gate 24, a NAND gate 26, an AND gate 28 or an OR gate 30, that is associated with many of the stages. In such prior art gray code counters, the combined logic circuitry for each binary stage usually occupies about as much surface area on a chip as occupied by a D-type flip-flop.
With the continuing advances in microfabrication technologies, there is less and less space available on a chip to include circuitry, such as digital binary counter logic. In addition, it is preferable to have a digital binary counter proximate to a device from which it receives an input signal so as to reduce propagation delay. For example, in the field of FPA chip manufacture, a digital counter needs to be as small as possible so that it can be placed within the portion of FPA chip surface area allocated to the pixel it is monitoring, rather than on the periphery of the FPA chip. If the counter occupies too much chip surface area, the portion of the FPA chip surface area allocated to an individual pixel would increase, thereby decreasing resolution for the FPA chip. Also, if the digital counter occupies too much chip surface area, a counter having a shorter count range may need to be implemented, which would require higher output signal rates.
It is also known that the surface area on a chip that a digital counter will occupy is a function of the process used to manufacture the counter on the chip. As chips become smaller and smaller to require finer geometries for manufacture of circuitry, the cost of manufacturing such circuitry increases. By reducing the amount of circuitry on a chip, such as the size of the circuitry of a digital binary counter required to be included on a chip, substantial cost savings and implementation advantages can be achieved.
Therefore, there exists a need for a digital binary counter that can be sampled asynchronously with a minimum of read error and requires a minimum of logic circuitry in its implementation.